Technologies
coming soon
coming soon
QUALITY STANDARDS
STAY UPDATED
At high frequencies, the PCB itself becomes part of the circuit. Controlled impedance is what keeps signal integrity intact as data rates climb — and Sunstone can help you get it right from the first design to final test.
Impedance tolerance delivered
Most common single-ended target
Most common differential pair target
Design support and fabrication
Impedance is a measure of how a transmission line resists the flow of alternating current. When the impedance of a trace doesn't match the impedance of the driver or receiver it connects to, signal reflections occur — and at high frequencies, those reflections degrade data integrity, increase noise, and can cause functional failures that don't show up at lower speeds.
Controlled impedance is the discipline of designing and fabricating PCB traces so their characteristic impedance hits a specified target — typically 50Ω for single-ended signals and 100Ω differential for high-speed pairs. It's not just about trace width: dielectric constant (Dk), dielectric thickness, copper weight, trace spacing, and reference plane geometry all interact to determine the final impedance value.
Getting it right requires coordination between design decisions and fabrication parameters. Sunstone supports both sides — whether you're working out your stack-up early in the design process or troubleshooting signal integrity problems on an existing board.
We help you build a layer stack-up that achieves your target impedance, balancing dielectric thickness, material Dk, and copper weight for your specific design requirements
Single-ended and differential pair traces both require specific width and spacing to hit impedance targets. We calculate the trace geometries that work for your stack-up.
Strategic placement of components, vias, and coupling capacitors directly affects signal integrity. We advise on placement decisions that minimize impedance discontinuities.
Propagation delay is a function of trace length and effective Dk. We adjust length matching across differential pairs and parallel buses to keep signals in time.
The effective dielectric constant seen by a signal depends on the materials and geometry of the stack-up. We calculate this accurately so your impedance model reflects real fabrication conditions.
Sunstone delivers controlled impedance builds to ±5% tolerance, verified by coupon testing on production panels — the standard required by most high-speed and high-reliability specifications.
The impedance a transmission line presents to a traveling wave, determined by trace geometry and surrounding dielectric. Must match source and load impedance to avoid reflections.
The material property that determines how fast signals propagate and how wide traces need to be for a given impedance target. Varies by material, frequency, and glass style.
Two traces carrying equal and opposite signals. Differential impedance — typically 100Ω — is influenced by both individual trace width and spacing.
The time it takes a signal to travel from one end of a trace to the other. Determined by trace length and effective Dk.
| Specification | Details |
|---|---|
| Impedance tolerance | ±5% (verified by TDR coupon testing) |
| Trace types supported | Single-ended, differential pair, coplanar waveguide, microstrip, stripline |
| Stack-up assistance | Available — Sunstone engineers can help design or validate your stack-up |
| Effective Dk calculation | Provided for your specific material and stack-up configuration |
| Length matching support | Available for differential pairs and parallel bus interfaces |
| Via and component placement guidance | Available as part of design support |
| Coupling capacitor placement | Guidance available for AC-coupled high-speed interfaces |
| Materials supported | Standard FR-4, High Tg FR-4, low-loss high-speed laminates, RF materials |
| Engagement point | Early design, pre-production review, or troubleshooting existing boards |
The best time to establish controlled impedance requirements is before your stack-up is locked. Changes to dielectric thickness, material selection, or copper weight are straightforward at this stage — expensive after the fact. Share your layer count, target impedances, and data rates and we can help you build a stack-up that works.
If you’ve designed your board with specific trace widths for impedance control, a pre-fab review confirms that your geometry assumptions match what Sunstone’s process will actually produce. Catching a mismatch here avoids a respun board.
Signal integrity issues on assembled boards often trace back to impedance discontinuities — via stubs, reference plane splits, or trace geometry errors. If you’re chasing a problem on an existing design, our team can help diagnose whether the board fabrication is within spec or whether the issue lives in the design itself.
Both. Trace width and stack-up geometry are design variables, but the actual impedance a fabricated trace achieves depends on how closely the fab hits the target dielectric thickness, the actual Dk of the material lot, and how precisely trace width is controlled during etching. That's why controlled impedance is a fabrication specification, not just a design intent — and why coupon testing is used to verify that the process delivered what was designed. A ±5% tolerance means the fab has committed to achieving your target within that range, not just approximating it.
At minimum: layer count, board thickness, target impedance values (and which layers they apply to), material preference if you have one, copper weight, and your target data rates. If you already have a stack-up in mind, share it and we can verify the geometry or suggest adjustments. The more context you provide about your interface speeds and signal types, the more useful the guidance we can give back.
Microstrip traces run on the outer layer of the board with dielectric on one side and air on the other. Stripline traces are buried between two reference planes. Microstrip is easier to fabricate and inspect but more susceptible to radiation and crosstalk. Stripline provides better shielding and more consistent impedance but adds cost and limits via routing flexibility. The right choice depends on your frequency range, EMI requirements, and layer budget — and the impedance calculation for each structure is different.
Yes — vias create impedance discontinuities that become significant at high data rates. A via has capacitance (from the pad) and inductance (from the barrel), and any unused portion of the via below the signal layer — called a stub — creates a resonance that can cause signal reflections at specific frequencies. For designs above a few Gbps, via stubs often need to be addressed through back-drilling, blind vias, or careful via design. This is one of the reasons component placement and via strategy are part of a complete controlled impedance discussion, not just trace routing
Yes. It's common to specify controlled impedance on the signal layers carrying high-speed interfaces while leaving power and ground planes — and any low-speed signal layers — unspecified. Your fabrication notes should clearly call out which layers have controlled impedance requirements, what the target impedance is on each, and what trace width was used so the fab can verify the design intent matches their process output.
Share your layer count, data rates, and Impedance targets and we'll help you get there.