UHDI boards are getting more common. Footprints are shrinking. Tolerances are tighter than ever. If you're designing for ultra-high density interconnect, the strip-etch-strip (SES) process deserves your attention, because the way you design directly affects how well it works. Here's what happens and what it means for your layout decisions. 

How SES Works 

After pattern plating, your panel carries copper traces and through-holes protected by a layer of electrolytic tin. The SES process has three stages: strip the photoresist, etch the exposed copper, strip the tin. Each stage introduces variables. Each variable can affect your finished trace geometry. 

The Strip 

Photoresist comes off in an alkaline bath. When it goes cleanly, you're in good shape. When it doesn't, you have problems. Over-plating during the previous pattern plating step can create a mushroom cap effect over the photoresist, narrowing the gaps between conductors and making it much harder to fully clear the resist underneath. Resist left on the panel can block the etch and create shorts. You can't control the plating process from your desk, but you can design to reduce the risk. Leave adequate spacing between traces. Be conservative about copper thickness requirements, especially inside plated through-holes. The more copper in the system, the higher the chance of over-plating. 

The Etch 

This is where trace geometry gets decided. The etchant attacks exposed copper both vertically and laterally, undercutting the tin-protected traces as it works. That lateral undercutting narrows your traces and can produce a trapezoidal cross-section rather than the clean rectangular shape you drew. The fix is to design with an etch compensation factor, meaning your traces on the film should be drawn slightly wider than the final required dimension. Your fabricator can give you specific compensation values based on their process. If you're designing for controlled impedance, this matters a lot. 

Don't assume your DRC will catch everything here. Most DRC tools flag traces that are too close together, but they won't flag large gaps between traces. Those gaps can create crosstalk and signal integrity problems that only show up after fabrication. Review your layouts manually for spacing anomalies, not just minimum clearance violations. 

The Second Strip 

Once etching is complete, the tin comes off in a nitric acid bath. Tin has to go because it can grow tin whiskers over time, dendritic structures that cause failure in the field. Residual tin also interferes with surface finish application. The nitric acid is aggressive but selective. Copper reacts with it, so the panel can't stay in the bath too long. Timing and chemistry control matter here, and again, your design affects how much margin the process has to work with. 

Bottom Line for Designers 

You don't need to run an etch line to understand SES. But you do need to understand that the process is reactive, and it will respond to what you put in front of it. Trace width, spacing, copper density, and via design all affect how cleanly the process completes. If you want to see it in action, visit your fab and watch a panel run. 

There's no substitute for seeing how the variables play out in real time. Questions? We're happy to talk through your UHDI design before it goes to fabrication. That conversation is a lot more productive than a yield discussion after the fact.