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When standard trace widths aren't small enough and layer counts keep climbing, UHDI is the path forward. What follows covers what it is, when it makes sense, and what ASC Sunstone can build.
Ultra-High Density Interconnect refers to PCB fabrication using line widths and spaces measured in microns, far finer than traditional subtractive-etch processes can reliably achieve.
Where conventional processes typically bottom out around 3–4 mil (75–100 micron) traces, UHDI pushes into the 20-micron range using a semi-additive process (SAP) rather than etching away copper. Instead of removing material, copper is selectively deposited exactly where it's needed. delivering tighter tolerances, cleaner geometries, and more consistent results at extreme feature sizes.
The result: smaller boards, fewer layers, better signal integrity, and new design possibilities that weren't feasible before.
Reduce board footprint and weight vs conventional HDI designs.
Fine traces enable more routing in less space.
High aspect ratios and tight impedance control (<5%).
Better performance for RF at fine geometries.
Materials will be listed here
Combine UHDI with standard layers efficiently.
| Specification | Value / Range |
|---|---|
| Minimum line width Minimum line space Near-term roadmap Board types supported Material compatibility Impedance tolerance Microvia diameter | 20 microns (0.8 mil) current 20 microns (0.8 mil) 12.5 micron (0.5 mil) trace and space Rigid, Flex, Rigid-Flex Works with all standard material types <5% for all line widths, including 3 mil and above Down to 75 microns with copper fill |
| Hybrid construction | UHDI on select layers; standard subtractive on others |
| Outer layers | UHDI features supported on outer layers |
| Plated through holes Max layer count | Compatible with UHDI outer layer designs No hard limit |
| Trace-to-pad spacing (mask-defined pads) | As low as 25 microns |
| Trace-to-pad spacing (copper-defined pads) | Minimum 50 microns, preferably 75 microns |
| Inner layer copper-to-copper spacing | 25 microns or below possible |
| Via-in-pad (VIPPO) | Recommended on non-SAP layers; see design notes below |
| Copper-filled microvia for VIPPO | 3–4 mil diameter, aspect ratio ≤ 1:1 |
| Biocompatible conductor options | Gold and other noble metals (copper/nickel-free possible) |
Not every board needs UHDI, but for these scenarios, it's often the most practical path:
SAP works across a wide range of feature sizes. There are signal integrity benefits to the semi-additive process even at larger geometries, it isn't limited to UHDI applications.
No. Hybrid constructions are the most common approach. Signal layers use UHDI where fine features are needed; layers with only larger geometries use traditional subtractive-etch to keep costs in check. You choose where each technology is applied.
Yes. Semi-additive processes are proven fabrication methods. In fact, reducing layer count and lamination cycles through better routing density can improve reliability compared to complex conventional stackups.
SAP processing has higher per-step costs, but the total board cost often comes down because you're using fewer layers, fewer lamination cycles, and a simpler overall design. For complex, high-performance boards the math often favors UHDI.
VIPPO structures are best placed on non-SAP layers. If you need VIPPO alongside ultra-fine lines, use a copper-filled microvia (3–4 mil diameter, aspect ratio ≤1:1) to transition to the next layer. If the top and bottom don't need UHDI features, a buried via structure with fill and plate-over is another option.
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