QUALITY STANDARDS
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Your board has copper. It's been plated, etched, and inspected. Now it needs to be protected and documented. Solder mask and legend are the final steps before your PCB is ready for assembly, and both are more design-sensitive than most designers realize.
Here's what happens at this stage and where your decisions make a difference.
Before solder mask goes on, the board gets inspected. For simpler designs, a trained inspector under magnification is sufficient. For higher-density boards, or any build requiring better than Class 2 IPC-A-600 compliance, automated optical inspection (AOI) is the right call. AOI performs a near pixel-to-pixel comparison between the physical board and your original design data.
Your design files directly affect how well AOI works. Bloated files with unnecessary data slow the process and introduce room for error. Send clean data. Strip out anything that isn't needed. It's a small thing that has a real impact on inspection speed and accuracy.
Solder mask is the protective polymer coating that covers the copper you don't want exposed. It keeps solder where it belongs during assembly, protects traces from oxidation and environmental damage, and provides electrical insulation between conductors.
Application is typically liquid photo-imageable (LPI), meaning the mask is applied as a liquid, exposed to UV light through a film or direct imaging, and then developed, leaving openings only where you need them: pads, vias you want exposed, test points.
Solder mask expansion matters. The opening in the mask around each pad needs to be sized correctly. Too small and you risk mask-on-pad, which causes solderability problems. Too large and you reduce the insulation between adjacent pads, which is a real concern at tight pitches.
Mask-defined versus copper-defined pads is a decision with downstream consequences. On fine-pitch components, mask-defined pads use the mask opening to set the effective pad size. Copper-defined pads rely on the copper geometry. Know which your design requires and communicate it clearly.
Sliver conditions are a fabrication risk. If your layout creates thin slivers of solder mask between closely spaced pads or features, those slivers can lift or crack. Review your layout for sliver conditions, particularly around fine-pitch BGAs and QFNs.
Tented vias need to be called out explicitly. If you want vias covered by solder mask rather than left open, specify it. Assumptions here cause problems at assembly.
Legend, also called silkscreen, is the ink layer that documents component placement, reference designators, polarity markers, and other information your assembly team needs. It doesn't affect electrical performance, but a poorly executed legend creates real problems on the production floor.
Keep reference designators readable at the assembled board scale. Tiny text that looks fine on screen becomes unusable under magnification after components are placed.
Don't put legend over exposed pads or vias. Ink on a solderable surface causes solderability failures. Your CAD tool may not flag this automatically, so check it manually.
Orient polarity markers and pin-1 indicators so they remain visible after the component is placed. If your marker is under the body of the IC, it's useless.
Use a consistent text height and stroke width across the board. Mixed legend styles are a sign of a design that wasn't reviewed as a whole.
Solder mask and legend sit at the end of the fabrication sequence, but they're not an afterthought. Mask design affects assembly yield. Legend quality affects production efficiency and long-term maintainability of the board.
Get these details right in the layout and you reduce the chance of a conversation you don't want to have after the boards arrive.
Have questions about solder mask specifications or legend requirements for your next build? Reach out. We'd rather sort it out before fabrication than after.
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